• Your shopping cart is empty!

  • JEDEC JEP147
Provide PDF Format

Learn More

JEDEC JEP147

  • PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)
  • standard by JEDEC Solid State Technology Association, 10/01/2003
  • Publisher: JEDEC

$27.00$53.00


This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component.

Product Details

Published:
10/01/2003
Number of Pages:
11
File Size:
1 file , 260 KB

Related Products

JEDEC JESD78D

JEDEC JESD78D

IC LATCH-UP TEST..

$37.00 $74.00

JEDEC JESD 82-28A

JEDEC JESD 82-28A

FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx)..

$82.00 $163.00

JEDEC EIA 323 (R2002)

JEDEC EIA 323 (R2002)

AIR-CONVECTION-COOLED, LIFE TEST ENVIRONMENT FOR LEAD-MOUNTED SEMICONDUCTOR DEVICES..

$26.00 $51.00

JEDEC JESD94B

JEDEC JESD94B

APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY..

$40.00 $80.00