Provide PDF Format

JEDEC JEB 5-A (R1984)

METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITS
standard by JEDEC Solid State Technology Association, 01/01/1970
Publisher: JEDEC

$40.00$80.00

Description

The purpose of this bulletin is to recommend for use in the rating of semiconductor logic gating microcircuits which use the binary states to represent and process logic information. Both static and dynamic measurements are covered.

Product Details

Published:: 01/01/1970
Number of Pages:: 44
File Size:: 1 file , 1.4 MB

Related Products

JEDEC JESD78D

IC LATCH-UP TEST..

$37.00 $74.00

JEDEC JESD 82-28A

FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx)..

$82.00 $163.00

JEDEC EIA 323 (R2002)

AIR-CONVECTION-COOLED, LIFE TEST ENVIRONMENT FOR LEAD-MOUNTED SEMICONDUCTOR DEVICES..

$26.00 $51.00

JEDEC JESD94B

APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY..

$40.00 $80.00